\doxysection{LL\+\_\+\+UTILS\+\_\+\+PLLInit\+Type\+Def Struct Reference}
\hypertarget{struct_l_l___u_t_i_l_s___p_l_l_init_type_def}{}\label{struct_l_l___u_t_i_l_s___p_l_l_init_type_def}\index{LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}}


UTILS PLL structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+ll\+\_\+utils.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a129ade94ff1ceb47b364505f37a0e054}{PLLM}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_aef85256f3086593ffa6ee4ec043ed150}{PLLN}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a0075fd05dc3f068a9d485ededb5badec}{PLLP}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_abd8e99d9901955a320dfd8ced9e2b156}{FRACN}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_ac397dc6e3125c0f92056dc1104223743}{VCO\+\_\+\+Input}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a4125ce55eef8119a9760c053e43b2e35}{VCO\+\_\+\+Output}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
UTILS PLL structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_abd8e99d9901955a320dfd8ced9e2b156}\index{LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}!FRACN@{FRACN}}
\index{FRACN@{FRACN}!LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{FRACN}{FRACN}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_abd8e99d9901955a320dfd8ced9e2b156} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+PLLInit\+Type\+Def\+::\+FRACN}

Fractional part of the multiplication factor for PLL VCO. This parameter can be a value between 0 and 8191

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+PLL1\+\_\+\+Set\+FRACN(). \Hypertarget{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a129ade94ff1ceb47b364505f37a0e054}\index{LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}!PLLM@{PLLM}}
\index{PLLM@{PLLM}!LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLM}{PLLM}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a129ade94ff1ceb47b364505f37a0e054} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+PLLInit\+Type\+Def\+::\+PLLM}

Division factor for PLL VCO input clock. This parameter must be a number between Min\+\_\+\+Data = 0 and Max\+\_\+\+Data = 63

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+PLL1\+\_\+\+Set\+M(). \Hypertarget{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_aef85256f3086593ffa6ee4ec043ed150}\index{LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}!PLLN@{PLLN}}
\index{PLLN@{PLLN}!LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLN}{PLLN}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_aef85256f3086593ffa6ee4ec043ed150} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+PLLInit\+Type\+Def\+::\+PLLN}

Multiplication factor for PLL VCO output clock. This parameter must be a number between Min\+\_\+\+Data = 4 and Max\+\_\+\+Data = 512

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+PLL1\+\_\+\+Set\+N(). \Hypertarget{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a0075fd05dc3f068a9d485ededb5badec}\index{LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}!PLLP@{PLLP}}
\index{PLLP@{PLLP}!LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLLP}{PLLP}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a0075fd05dc3f068a9d485ededb5badec} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+PLLInit\+Type\+Def\+::\+PLLP}

Division for the main system clock. This parameter must be a number between Min\+\_\+\+Data = 2 and Max\+\_\+\+Data = 128 odd division factors are not allowed

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+PLL1\+\_\+\+Set\+P(). \Hypertarget{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_ac397dc6e3125c0f92056dc1104223743}\index{LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}!VCO\_Input@{VCO\_Input}}
\index{VCO\_Input@{VCO\_Input}!LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{VCO\_Input}{VCO\_Input}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_ac397dc6e3125c0f92056dc1104223743} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+PLLInit\+Type\+Def\+::\+VCO\+\_\+\+Input}

PLL clock Input range. This parameter can be a value of RCC\+\_\+\+LL\+\_\+\+EC\+\_\+\+PLLINPUTRANGE

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+PLL1\+\_\+\+Set\+VCOInput\+Range(). \Hypertarget{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a4125ce55eef8119a9760c053e43b2e35}\index{LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}!VCO\_Output@{VCO\_Output}}
\index{VCO\_Output@{VCO\_Output}!LL\_UTILS\_PLLInitTypeDef@{LL\_UTILS\_PLLInitTypeDef}}
\doxysubsubsection{\texorpdfstring{VCO\_Output}{VCO\_Output}}
{\footnotesize\ttfamily \label{struct_l_l___u_t_i_l_s___p_l_l_init_type_def_a4125ce55eef8119a9760c053e43b2e35} 
uint32\+\_\+t LL\+\_\+\+UTILS\+\_\+\+PLLInit\+Type\+Def\+::\+VCO\+\_\+\+Output}

PLL clock Output range. This parameter can be a value of RCC\+\_\+\+LL\+\_\+\+EC\+\_\+\+PLLVCORANGE

This feature can be modified afterwards using unitary function LL\+\_\+\+RCC\+\_\+\+PLL1\+\_\+\+Set\+VCOOutput\+Range(). 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__ll__utils_8h}{stm32h7xx\+\_\+ll\+\_\+utils.\+h}}\end{DoxyCompactItemize}
